What is leaf layout

They are repeatable layout designs that can be reused in many different regions of the chip.

They can be made out of one polygon—i.e., contact cells; can be made out of three polygons—i.e., contact cells made with the surrounding layers (metal1, metal2, via12); or can be a complete circuit—i.e., inverter, NAND, flip-flop.

They may have different versions of the layout for one version of the schematic because an inverter of equivalent size in the I/O region will have a different cell environment or interface than one in the memory region of the chip.

Any group of polygons using a standard interface makes sense to be made as a leaf cell. For example, a library of logic gates all generally have a standard power supply layout interface, and so it makes sense for each of the gates to be a cell. If a design of multiple logic gates is to be implemented, it is not recommended that the design be done at the transistor level. Making logic gate cells first is preferred.

If global changes are required to a design, it is much easier if cells are used. Imagine updating a design with 100 inverters. Consider the case of one design with an inverter cell instantiated 100 times versus another “flat” design with 200 transistors connected as 100 inverters. A change is required to all 100 inverters. In the case of the inverter cell design, the inverter cell is updated. Depending on the change required in the 200-transistor case it is likely that it would be more efficient to start the design over from scratch using cells than to try to update all 200 transistors.

Conversely, using our 100-inverter example again, we must be very careful if only 1 of the 100 cells requires updating. We cannot change the inverter cell without affecting the other 99. In this case a second inverter cell is required that reflects the required updates and we replace the one outdated inverter with the new one.

Every cell in a design needs a unique identifier even if it is a second instantiation of an already designed cell. In our example of the design with 100 instantiations of a cell called INV, we need to identify each one uniquely (i.e., 48 LAYOUT DESIGN INV001, INV002) and the identification of the cell should match the name that is used in the circuit design if there is an electrical correspondence. This instance name is needed to differentiate each of the physically identical INV cells. This is very useful in our example of changing 1 out of the 100 inverters, as we can use the instance name to identify the outdated inverter.

Cells can be flipped and rotated much more easily than groups of polygons.

If a symmetrical layout is required, one cell representing one-half of the design is all that is needed, and this techniques guarantees that the resulting layout is perfectly symmetrical!

Cells can be scaled, although this is risky because of issues with polygon coordinates becoming off grid.

Computer screen redraw resources is minimized using cells as all polygons within a cell need not be shown. It is often necessary to show only the key interface polygons and leave the details of the cell hidden.

Cells can be “arrayed” to save more computer resources. An array can be thought of as the definition of a matrix of cells. For example let’s consider the case of implementing a 10 ¥ 10 matrix of memory cells. We are given a single memory cell as the leaf cell. One option is to instantiate the memory cell 100 times (this results in 100 X,Y coordinates, or 200 numbers that not only must be stored—we have to generate them as well!). A better option is to define an array that requires an X,Y origin, an X,Y offset, and the number of rows and columns (six numbers!).

The use of cell arrays also reduces computer screen redraw time. For example, certain software packages have options to display only the border cells of an array. Another option would be to display only the corner cells.

Hierarchical layout verification tools can take advantage of the repeated use of a smaller number of cells versus many individual ones. In our example of a design with 100 instantiations of a single inverter cell, conceptually a layout verification tool needs only to verify the inverter cell once and then check how each of these cells interfaces to each other. This approach is much faster than verifying the case of 200 transistors connected as inverters.