what is device leakage

In deep submicron CMOS technologies, the gate insulator thickness has reduced to 2nm and below on high performance FETs, this translates to the width of ten silicon atoms. At such thicknesses, tunnelling currents through the gate are becoming significant. In deep submicron technologies, several gate thicknesses are often available. On a 90nm process, the gate leakage with a 1.4nm device may be around 50 nA/um2 whereas for a 2.5nm device it is effectively zero. In analog circuits where gate leakage is important, for example sample and hold circuits or low current circuits, it may be possible to simply substitute thicker FET devices. Of course a penalty is incurred with lower performance in terms of transconductance and speed but this may well be acceptable in such circuits. Alternatively, the gate leakage can be compensated for with additional circuitry, for example using other devices to track and balance the leakage. Fortunately, this tunnelling current can be accurately modelled and therefore detected at the circuit design stage.
At the chip level, the increased leakage currents can be a serious issue for static power consumption and IDDQ testing and this is well documented in the literature. The gate dielectric forms the basis of most on-chip capacitance devices with the thinner gates obviously providing the greatest capacitance per unit area. The leakage current of such capacitors can approach 0.5A/cm2 and this highlights the problem of static current on large chips. The use of such capacitors in analog circuits in such critical areas as phase locked loop filters requires careful consideration of the leakage.