what is chip floor planning

Floorplanning is the process of identifying structures that should be placed
together and allocating space for them so as to meet the conflicting goals of available
space (cost of the chip), required performance, and the desire to have every
block connect seamlessly to everything else.
In most chips, the smallest design is also the highest performance design.
Therefore, area and speed are characteristics that go hand-in-hand. Ablock or chip
that is small in area has shorter interconnect lines, less routing, faster end-to-end
signal paths, and even faster and more consistent place-and-route times.
Floorplanning is methodology that should result in a smaller design because
the design is planned efficiently by combining the expertise of the layout designer in
partitioning the circuitry and the optimization algorithms in the floorplanning tool.