vlsi tutorial


InfoPad Project in Berkeley
Design Technology Warehouse in Berkeley
The Eindhoven Universityof Technology
Hardware/Software Codesign
Univ. of California, Berkeley
Univ. of Illinois, U-C
Standford University
USC (lower power, Prof. Pedram)
Univ. of Tennessee at Knoxville (MCM, Prof. Bouldin)
Courses on microelectronic systems
Univ. of Virginia
North Carolina State Univ.
Analog VLSI & Robotics Lab
Circuits, Systems and Artificial Neural Networks Laboratory
HUT Circuit Theory Laboratory
Integrated Circuits Laboratory
Integrated Systems Laboratory
Koch Lab
Laboratory for Materials, Device and Circuit Simulations
Microelectronics And Computer Systems
Microsystems Prototyping Laboratory
Microsystems Technology Laboratories
Semiconductor Subway
Integrated Circuits Laboratory
List of Universities with Fabrication Facilities
Microtechnology Laboratory
NCSU’s CAD Benchmarking Lab
Northwestern University’s VLSI Algorithmic Design Lab
Reconfigurable Computing Lab
Sensory Communication and Analog VLSI Laboratory
Solid State Electronics Laboratory
Tima-Cmp Laboratory
TUT’s Computer Engineering Laboratory
VLSI-FPGA Design & Test Laboratory
VLSI and CAD Lab
VLSI Design Automation Lab
VLSI Design Lab
VLSI System Architecture Lab (colorado state)
VLSI Systems Lab
VHDL projects
PLD Links
Index: VHDL, Verilog and SystemC Simulation Tools from Blue Pacific.
Download VHDL Similulator
Abstracts DAC 96
33rd Design Automation Conference Proceedings
SIGDA Proceeding Archives
ACM Digital Library Search
Synplicity: Home
FPGA Information
The FPGA Database
The RPM Project: Hardware Emulation of Multiprocessor Systems
RPM Project: Papers & Technical Reports
GSRC People
ResearchIndex: The NECI Scientific Literature Digital Library
ResearchIndex good research papers from nec
Rapid Hardware Prototyping On RPM-2: Methodology And Experience – Dubois, Jeong, Song, Moga (ResearchIndex)
The British Library
Welcome to the ALIA home page
University of Illinois at Urbana-Champaign
Scott Hauck – UWEE Faculty
Logic Partitioning
Multi-FPGA Systems & Rapid-Prototyping
ACM Digital Library: International Symposium on Field Programmable Gate Arrays
Index of /pubs/contents/proceedings/series/
Virtual Wires
Virtual Wires Published Papers
Doulos HDL Associates
SILOS III from Simucad
Verilogger Pro from SynaptiCAD Inc.
SMASH from Dolphin Integration

Berkeley Spice [ 3f5 rpm
Alliance VHDL
Structural Verilog Compiler
VERIWELL : A verilog Simulator
MAGIC Layout Tool
CALTECH – Chipmunk System
Ptolemy II (Ptolemy II is a set of Java packages supporting heterogeneous, concurrent modeling and design.)

Verilog On-Line Tutorial, by Dr. Daniel Hyde
Verilog On-Line Mannual, by Prof. Gerrard Blair
Verilog Introduction for Digital Design
Rajesh Bawankule’s Verilog and EDA Page
Alternate Verilog FAQ.
Celia’s Verilog & EDA page
Project VeriPage (PLI resources)
Veripool: Public domain verilog resources
VHDL Links
Begining VHDL: Class Notes by Zainalabedin Navabi, Northeastern University.
VHDL Code Land (VCL) Page.
VHDL International Home Page
VHDL International Users Forum (VIUF)
VHDL Validation Home Page
FAQ comp.lang.vhdl
VHDL Models
Microprocessor / Microcontroller
Great Microprocessors
CPU Central, Uncensored
Computer Design, OnLine
Intel Microprocessors
Intel Architechture Lab’s

Good research papers from DAC conference

TUTORIAL 1) ESL Design Methodology Using SystemC
Organizer: Francine Bacchini – ThinkBold Corporate Communications, San Jose, CA
Speakers: Wolfgang Rosenstiel – Univ. of Tuebingen, Tubingen, Germany
Jack Donovan – ESLX, Inc., Austin, TX
Maurizio Vitale – Philips Semiconductors, Pittsburgh, PA
Laurent Maillet-Contoz – STMicroelectronics, Crolles, France
Mike Meredith – Forte Design Systems, San Jose, CA
Vincent Viteau – Summit Design, Inc., Cedex, France
TUTORIAL 2) Practical Aspects of Coping with Variability: An Electrical View
Organizer: Chandu Visweswariah – IBM Corp., Yorktown Heights, NY
Speakers: Xi-Wei Lin – Synopsys, Inc., Mountain View, CA
Bora Nikolic – Univ. of California, Berkeley, CA
Peter A. Habitz – IBM Corp., Burlington, NC
Riko Radojcic – Qualcomm CDMA Technologies, San Diego, CA
TUTORIAL 3) Real DFM Solutions, Tools, Methodologies, and Successes
Organizer: Andrew B. Kahng – Univ. of California at San Diego, La Jolla, CA
Speakers: Nagaraj NS – Texas Instruments Inc., Dallas, TX
Jean-Pierre Schoellkopf – STMicroelectronics, Crolles, France
Mike Smayling – Applied Materials, Sunnyvale, CA
Ban P. Wong – Chartered Semiconductor, Milpitas, CA
Andrew B. Kahng – Univ. of California at San Diego, La Jolla, CA
TUTORIAL 4) Surviving and Thriving in the World of Chip and Package Co-Design
Organizers: Chung-Kuan Cheng – Univ. of California at San Diego, La Jolla, CA
Howard Chen – IBM Corp., Yorktown Heights, NY
Speakers: David Flynn – ARM Ltd., Cambridge, UK
Paul Harvey – IBM Corp., Austin, TX
Howard Chen – IBM Corp., Yorktown Heights, NY
Lei He – Univ. of California, Los Angeles, CA
Chung-Kuan Cheng – Univ. of California at San Diego, La Jolla, CA
Kaushik Sheth – Rio Design Automation, Inc., Santa Clara, CA
TUTORIAL 5) – SystemVerilog: Language Tutorial and Industrial Verification Experience
Organizer: Johny Srouji – IBM Corp., Austin, TX
Speakers: Johny Srouji – IBM Corp., Austin, TX
Karen Pieper – Synopsys, Inc., Sunnyvale, CA
Tom Fitzpatrick – Mentor Graphics Corp., Groton, MA
John Havlicek – Freescale Semiconductor, Inc., Austin, TX
Matt Maidment – Intel Corp., Portland, OR
Cliff Cummings – Sunburst Design Inc., Portland, OR
TUTORIAL 6) Tools for Hybrid Embedded Systems: Modeling, Verification, and Design
Organizer: Luca Carloni – Columbia Univ., New York, NY
Speakers: Hilding Elmqvist – Dynasim AB, Lund, Sweden
George Pappas – Univ. of Pennsylvania, Philadelphia, PA
Pieter J. Mosterman – The MathWorks, Inc., Natick, MA
Alessandro Pinto – Univ. of California, Berkeley, CA
Alberto Sangiovanni-Vincentelli – Univ. of California, Berkeley, CA
TUTORIAL 7) From Basic to Advanced Techniques for Silicon Debug and Diagnosis
Organizer: Srikanth Venkataraman – Intel Corp., Hillsboro, OR
Speakers: Srikanth Venkataraman – Intel Corp., Hillsboro, OR
Miron Abramovici – DAFCA Inc., Framingham, MA
Robert Aitken – ARM, Sunnyvale, CA
More 1 PANEL: How Will the Fabless Model Survive?
More 2 Special Session: Why Doesn’t My System Work?
More 3 Hierarchical Synthesis for Mixed-Signal Designs
More 4 Processor and Communication Centric SoC Design
More 5 Practical Applications of DFM
More 6 PANEL: The IC Nanometer Race: What Will It Take to Win?
More 7 Special Session: Bridging the System to RTL Verification Gap
More 8 Leakage, Power Analysis and Optimization
More 9 MPSoC Design Methodologies and Applications
More 10 Statistical Timing Analysis
More 11 PANEL: Entering the Hot Zone — Can You Handle the Heat and Be Cool?
More 12 Special Session: Reliability Challenges for 65nm and Beyond
More 13 Power Grid Analysis and Design
More 14 Advances in Formal Solvers
More 15 Gate Modeling and Model Order Reduction
More 16 Special Session: MPSoC Design Tools
More 17 Special Session: Highlights of ISSCC: Multimedia
More 18 Buffer Insertion
More 19 Testing and Validation for Timing Defects
More 20 Advanced Topics in Processor and System Verification
More 21 Software for Real-Time Applications
More 22 PANEL: Building a Standard ESL Design and Verification Methodology
More 23 Invited Session: CAD Challenges for Leading-Edge Multimedia Designs
More 24 Routing
More 25 The Test Bin
More 26 PANEL: Variation-Aware Analysis: Savior of the Nanometer Era?
More 27 Low Power and Ultra-Low Voltage Design
More 28 High-Level Exploration and Optimization
More 29 PANEL: Design Challenges for Next-Generation Multimedia, Game and Entertai
More 30 CAD for FPGAs
More 31 Secure Systems
More 32 Logic Synthesis 1
More 33 Low-Power, Thermal-Aware Architectures
More 34 Low Power System Level Design
More 35 Power-Constrained Design for Multimedia
More 36 Electrical and Thermal Issues in FPGAs
More 37 Special Session: Beyond Low-Power Design: Environmental Energy Harvesting
More 38 Communication-Driven Synthesis
More 39 Parallelism and Memory Optimizations
More 40 PANEL: Tomorrow’s Analog: Just Dead or Just Different?
More 41 Nanotubes and Nanowires
More 42 Simulation Assisted Formal Verification
More 43 Yield Analysis and Improvement
More 44 Approaches to Soft Error Mitigation
More 45 Design/Technology Interaction
More 46 PANEL: Building a Verification Test Plan: Trading Brute Force for Finesse
More 47 Special Session: More Moore’s Law and More than Moore’s Law
More 48 Formal Specification and Verification Testbench Generation
More 49 Analysis and Optimization Issues in NoC Design
More 50 Special Session: Key Technologies for Beyond the Die
More 51 Analog Design and Design Assistance
More 52 High-Performance Simulation of Transaction Level and Dataflow Models
More 53 Nano- and Bio-Chip Design
More 54 Logic and Sequential Synthesis
More 55 Low Power Circuit Design
More 56 Beyond-the-Die Circuit and System Integration
More 57 New Ideas in Analog/RF Modeling and Simulation
More 58 Advanced Methods for Interconnect Extraction, Clocks and Reliability
More 59 PANEL: DFM Where’s the Proof of Value?
More 60 Bounded Model Checking and Equivalence Verification
More 61 Test Response Compaction and ATPG
More 62 Placement
More 100 Decision-Making for Complex SoCs in Consumer Electronic Products
More 150 Tradeoffs and Choices for Emerging SoCs in High-End Applications