VLSI (Very Large Scale Integration) allows to integrate millions of transistors on one chip. Todays CMOS technologies makes it possible to build whole systems on a chip, which consist of processor cores, memories, digital and analog interfaces. IAIK contributes with solutions to secure such systems.
USBCRYPT crypto module with USB interface
The goal of the USB-Crypt project is to develop and integrate a powerful, but easily portable crypto module with an USB interface as a secure single chip IC. This IC module will contain all of the standard crypto algorithms like AES, DES, RSA, ECC and Hashing. It can then be mounted into an USB dongle like housing for universal use with an I&C equipment fitted out with an USB interface. The practical usability together with the system features will be tested by different security applications like: e-commerce, network security, data encryption and digital security. The overall security quality will be analyzed and certified by a Common Criteria evaluation.
IAIK is workpackage leader for Crypto Coprocessor Development. We are developing an AES module and Hash Algorithm coprocessor.
The AES (Advanced Encryption Standard) module encrypts and decrypts 128-bit blocks of incoming data at a very high bit-rate. To achieve the high throughput demands of the USB_Crypt device, we need to apply pipelining and parallel computation for calculation of the round function. Pipelining is used to keep critical paths short for high clock frequencies and parallel computation keeps the number of cycles per operation low. Pipelining of the rounds doesn’t help to improve throughput, if the module is used in modes of operation like Cipher Block Chaining (CBC) where the output of the last block is needed before the next block can be computed.
Our AES core architecture will be very flexible to provide modules for different applications in a very fast manner. For smart card application we would use a lower grade of parallelism to reduce die size to a minimum. Typical smart card processors kernels operate with relatively low clock frequency which allows to reduce the number of pipelining stages and increase throughput per cycle. With our AES core architecture we will be able to deal with both, low area and less throughput application or high throughput demands with less area requirement.
Our multi purpose Hash coprocessor can compute the Hash algorithms MD-5, RIPE MD-160, SHA-1 and SHA-256. A Hash Arithmetic Unit (HAU), a Programmable Logic Unit (PLU) in combination with a Register bank and a RAM block build up the Hash-core. As all the supported Hash algorithms are based on a 32-bit architecture, the core as well has a 32-bit structure. It is planned to provide a 32-bit interface for the USB_Crypt project, but we will also provide a 8-bit interface to use the module also in other controller families. Modular module-architecture makes it possible to re-use the core in various fields of application. For higher throughput demands it is possible to use up to four HAU blocks parallel to reduce the number of computation cycles to a minimum.