VLSI Project-Many bit per cell memories
In order to realize a very area-efﬁcient memory, several bits can be stored in a single memory cell. To store 2 or 3 bits per cell, 4 or 8 different symbols must be deﬁned, respectively. The symbols are then mapped to a physical quantity such as voltage or charge. Taking into account the decay over time of voltage and charge due to leakage currents, it is more convenient to map each symbol to a voltage or charge range. A many-bit per cell memory could consist of a 1T-1C storage cell, a digital-to-analog converter for the write operation, and a analog-to-digital converter for the read operation, in addition to standard memory peripheral circuits such as address decoders and output multiplexers. First of all, you conceive the many-bit per cell memory, i.e. you study and propose possible architectures, mapping schemes, etc. You then compare the different solutions, mainly in terms of area and power consumption, and pick the most favorable one. You then partition the memory in several blocks such as storage cell, converters, decoders, etc. and design each block in the most appropriate way. You will probably identify purely digital blocks which you may want to design in a top-down digital VHDL design ﬂow. Also, you will probably identify some mixed-signal blocks which you design at transistor level using Cadence. Of course, you will draw the layout of all mixed-signal blocks. As soon as all blocks have been designed and have met their speciﬁcations, they can be put together to form a many-bit per cell memory. The simulation of the whole memory would preferably be done at transistor level in Cadence, in order to include as much effects and details as possible. The memory will be manufactured in 130nm or 90nm CMOS technology. You will then design tests and perform them as soon as the chips comes back from the foundry.
Carrying out this project, you learn both the top-down digital VHDL design ﬂow and analog/mixedsignal integrated circuit design.