vlsi layout checklist

There are few things which should be taken care of from the very beginning of the layout. This
document lists them along with some additional tips:
01) Grid: It is very important to set the grid properly. In fact a wrongly set grid can render the
whole design useless because it cannot be correctly fabricated. Refer the design docu-ments
of the technology you are using and find out the acceptable value of the grid. It is
usually specified in terms of minimum grid size. You should set the grid to integer multi-ples
of this minimum value. Remember to set the grid right from the start of the layout,
and remember to set it correctly each time you open the file to modify the layout.
02) Guard Rings: Every transistor with its source and/or drain to be connected to the pads (to
the outside world) should be enclosed in a double guard ring (connected to AVSS &
AVDD respectively). This is to prevent the triggering of latch-up due to ESD conditions.
03) Antenna Errors: These DRC errors arise whenever there are long metal lines connected
directly to POLY. This can result in the destruction of the circuit during metal etching.
Therefore long metal lines must be avoided to be connected directly to POLY (Gates of
transistors, or Capacitors). In case long routing is required to be connected to a POLY, the
metal line must be broken at short distance from the POLY and a bridge inserted using
the other metal and vias. The routing can be continued with the previous metal thereafter.
The main objective is to prevent a long metal line of the same metal layer being con-nected
directly to the POLY.
04) Tip on Routing: The design documents usually list the ‘recommended’ widths of the
routings for respective metal and POLY layers. These are different from the ‘Minimum’
widths mentioned. In other words, unless it’s important to use the minimum width (lim-ited
space, or parasitic sensitive design), use the recommended width of the respective
layers. This ensures maximum reliability of the circuit.