vlsi interview 5

VLSI Interview question answers

Steps involved in designing an optimal padring

1. Make sure you have corner-pads, across all the corners of the padring, This is mainly to have the power-continuity as well as the resistance is less
2. Ensure that the Padring ful-fills the ESD requirement, Identifyh the power-domains, split the domains, Ensure common ground across all the domains.
3. Ensure the padring has ful-filled the SSN(Simultaneous Switching Noise) requirement.
4. Placing Transfer-cell Pads in the cross power-domains, for different height pads, to have rail connectivity.
5. Ensure that the design has sufficient core power-pads.
6. Choose the Drive-strenght of the pads based on the current requirements, timing.
7. Ensure that there is seperate analog ground and power pads.

8. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O’s.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with un-connected inputs, as they consume power if the inputs float.

9. Ensure that oscillator-pads are used for clock inputs.
10. In-case if the design requirement for source synchronous circuits, make sure that the clock and data pads are of same drive-strength.
11. Breaker-pads are used to break the power-ring, and to isolate the power-structure across the pads.
12. Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin.
13. In case if required , place pads with capacitance.

What is metastability and steps to prevent it.
Metastability is an unknown state it is neither Zero nor One.Metastability happens for the design systems violating setup or hole time requirements. Setup time is a requirement , that the data has to be stable before the clock-edge and hold time is a requirement , that the data has to be stable after the clock-edge. The potential violation of the setup and hold violation can happen when the data is purely asynchronous and clocked synchronously.

Steps to prevent Metastability.
1. Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain. Using Synchronizers, recovers from the metastable event.
2. Use synchronizers between cross-clocking domains to reduce the possibility from metastability.
3. Using Faster flip-flops (which has narrower Metastable Window).
12. what is local-skew, global-skew,useful-skew mean?
Local skew : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.
Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.
Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

what is meant by virtual clock definition and why do i need it?
Virtual clock is mainly used to model the I/O timing specification. Based on what clock the output/input pads are passing the data.

What are the various timing-paths which i should take care in my STA runs?

1. Timing path starting from an input-port and ending at the output port(purely combinational path).
2. Timing path starting from an input-port and ending at the register.
3. Timing path starting from an Register and ending at the output-port.
4. Timing path starting from an register and ending at the register.

What are the various components of Leakage-power?
1. sub-threshold leakage,….think of ths answer

What are the various yield-losses in the design?
The yield loss in the design is characterized by
1. Functional yield losses, mainly caused by spot defects , especially (shorts & opens)
2. Parametric yield losses, due to process variations.