VLSI architectures for Turbo Codes Adapted the Standard Mobile Communications WCDMA- vlsi thesis

Turbo Codes are a topic of great importance in communications systems. Therefore requires an analysis on architectures implemented so far. Simulations were performed in software of the turbo codes proposed by Berrou and established the 3GPP standard in order to monitor the performance of these varying different parameters. We carried out an analysis of the architecture and designs implemented so far and based on this we propose a new design with possible improvements in the design.
At present, the use of communication systems has grown in large quantities. For that reason requires communication systems make them more efficient data transmission, safe and with a better performance (faster transmission and more efficient use of bandwidth), in other words, communication systems more immune to noise and allowing transfers of large amounts of information. In 1948 Claude E. Shannon established the fundamental limits in transmission speeds in the systems of digital communications and led to the search for coding techniques for approaching the limit of this capacity . The Turbo Codes are one of the most important developments in recent years within the channel coding, which are reaching the limits of the theoretical capacity of channel posed by C. E. Shannon. They were proposed by the French engineers Claude Berrou and Alain Glavieux in Geneva, Switzerland in 1993 . Nowadays, the present standards of communications are incorporating turbo codes for the development of satellite links, in the space communication systems, the systems of third-generation telephony and also to increase the speed of data transmission in some versions of Wi-Fi networks. There are many groups in the world researching and working on the issues and big companies such as Sony, NEC, Nokia, Motorola and chip and hardware manufacturers as Comtech AHA, Altera, Xilinx, among others. In the country there is little development work on hardware implementation on turbo codes, which have an extensive field of research and applications. Some existing turbo codes implemented in hardware part of the intellectual property (IP) manufacturers, for example, Altera with “Turbo Encoder / Decoder MegaCore Function” implemented for the European standard WCDMA (3GPP TS 25,212) and Xilinx LogiCORE with, a turbo encoder and decoder for standard American CDMA2000 (TIA/EIA2002.2C).
There are little architectures on turbo codes especially focused standard for mobile communications. Developments at the level of hardware that we find are available only as intellectual property of the manufacturers.
The proposed study, design and implementation
reconfigurable hardware, the turbo decoding scheme defined
in the specifications of the standard WCDMA (3GPP TS
25,212 V7.2.0).
Implementation material of a turbo decoder reconfigurable hardware (FPGA architectures, Field Programmable Gate Array) with the specifications of the European standard WCDMA (3GPP TS 25,212) [4]. c. PARTICULAR OBJETIVES • Implement software scheme Turbo coding standard for WCDMA (3GPP TS 25,212). • Design architecture of a turbo decoder. • Developing a test bed. • Validation of architecture. In order to understand the operation of these, first we will see as it is its structure and operation. III. TURBO CODES TURBO ENCODER The general structure used in turbo encoders is shown in Fig. 1. The turbo encoder is formed by the concatenation parallel of two encoders Recursive Systematic Convolutional, RSC separated by an interleaver (see Fig. 1). The interleaver [5] is a pseudo-random mixer block defined by a permutation of N elements without repeating any of them, in other words, adjusts the order of the sequence in a form giving a different order sequence with the original.

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