vhdl building blocks
To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Using the schematic capture approach to design, this might be done with a block diagram editor. Every portion of a VHDL design is considered a block. A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. The interface description is like a pin description in a data book, specifying the inputs and outputs to the block. The description of the operation of the part is like a schematic for the block. For the remainder of the tutorial we will refer to a block as a design, even though a complete design may be a collection of many blocks interconnected.
The following is an example of an entity declaration in VHDL.
entity latch is
port (s,r: in bit;
q,nq: out bit);
The first line indicates a definition of a new entity, whose name is latch. The last line marks the end of the definition. The lines in between, called the port clause, describe the interface to the design. The port clause contains a list of interface declarations. Each interface declaration defines one or more signals that are inputs or outputs to the design.
Each interface declaration contains a list of names, a mode, and a type. In the first interface declaration of the example, two input signals are defined, s and r. The list to the left of the colon contains the names of the signals, and to the right of the colon is the mode and type of the signals. The mode specifies whether this is an input (in), output (out), or both (inout). The type specifies what kind of values the signal can have. The signals s and r are of mode in (inputs) and type bit. Next the signals q and nq are defined to be of the mode out (outputs) and of the type bit (binary). Notice the particular use of the semicolon in the port clause. Each interface declaration is followed by a semicolon, except the last one, and the entire port clause has a semicolon at the end.
All of the signals in the example are defined to be of the type bit. The type bit is a predefined type that can have two values represented by ‘0’ and ‘1’. This type is used to represent two level logic signals.
The second part of the description of the latch design is a description of how the design operates. This is defined by the architecture declaration. The following is an example of an architecture declaration for the latch entity.
architecture dataflow of latch is
signal q0 : bit := ‘0’;
signal nq0 : bit := ‘1’;
q0<=r nor nq0; nq0<=s nor q0; nq<=nq0; q<=q0; end dataflow; Go through the main tutorial http://www.gmvhdl.com/building.htm