verilog and vhdl

What is the difference between VHDL and Verilog?
On the surface, not that much. Both are research standards and are supported by all the major EDA vendors. Both can be used for designing ASICs and simulating systems. However, VHDL is altogether a grander language. Its support for system level modeling and simulation is far more comprehensive than Verilog. However, VHDL requires longer to learn and is not so amenable to quick-and-dirty coding. As a final thought many hardware engineers now have to know both languages due to the increasing use of IP (Intellectual Property) blocks, which may not be written in their “favourite” language.
Can I use VHDL for the analog part of a design?
Yes and No. Yes, there is a VHDL Analogue and Mixed Signal language (VHDL-AMS), based on VHDL 93, which allows modelling of both analogue and digital in the same language. However the idea of analogue synthesis is still in its early days, so currently you wouldn’t normally be able to go on and synthesize an analogue model written in VHDL-AMS. There’s a VHDL-AMS website at
How must I write VHDL to make it synthesisable?
Writing VHDL for synthesis is not particularly difficult, but you need to be disciplined, not only in your use of VHDL syntax but also your approach to writing VHDL for synthesis. It is this latter aspect which many engineers overlook; thorough training is really the only way to avoid making poor strategy decisions in writing synthesisable VHDL.
How many versions of VHDL are there?
There are four. The original release of the VHDL language occured in 1987 with the adoption of the Language Reference Manual as an research standard. In 1993, the research-1076 standard was modified and ratified and became known as VHDL’93. This is now widely supported. In 2000, the VHDL 1076 2000 Edition appeared – this fixed shared variables by introducing the idea of protected types. Finally, VHDL 1076-2002 appeared. This includes protected mode types, but also changes ports of mode buffer to make them more usable, along with some other small changes. In practise, VHDL 1076-1993 is the current flavour of VHDL which is widely supported by tool vendors.
Is VHDL going to be developed further?
You might have heard a lot about System Verilog, and wondered if VHDL is going to also
be developed? There is an activity to develop an improved VHDL, and VHDL-2008 was released
in January 2009.
A VHDL design can be moved to any tool or technology. Right?
On the face of it, this is true. VHDL was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving VHDL code from one simulator to another involves one or two minor changes to the VHDL. Two different synthesis tools may support two quite different VHDL subsets. This is particularly an issue for us at Doulos in developing our training courses, because we like to present a reasonably generic approach to writing VHDL for synthesis. This means that the VHDL we teach you is guaranteed to be more transportable between synthesis tools than it otherwise would be. Our pain is your gain! In addition because we are so aware of the differences between synthesis tools, this means that we emphasise the best way of writing VHDL to get the best from your synthesis tool.
Are there any tools to generate VHDL test benches automatically?
A number of tools provide simple “testbench templates”; even the Emacs editor VHDL mode can do this! For more advanced ways of writing testbenches, you might want to look at the so-called “Testbench Automation” tools, such as SystemC Verification Library, Verisity Specman, Chronology RAVE, and Synopys Vera. These tools involve learning another language of course. If you want to know how to write more complex testbenches (for instance to cope with data arriving in
a different order from the order it entered a device), have a look at our
Can you give me a measure of the productivity improvements I should expect from VHDL?
Well, do you believe the hype! Yes, ultimately there are considerable productivity gains to be had from using high-level design techniques in conjunction with synthesis technology, providing that your designs are: complex, amenable to synthesis, not dependent upon the benefits of a particular technology
Obviously, complex means different things to different people, but a good rule of thumb is that complex means the implementation part of the design process is considerably more awkward than the specification phase. Let’s face it, if the specification phase is significantly longer than the implementation phase, you need to put effort here, not into HLD. Of course, once you are benefiting from HLD productivity gains, the specification phase becomes more significant. OK, that’s HLD: VHDL is a HLD design entry language, so we would expect the use of VHDL with synthesis technology to improve productivity in the design process. However, you won’t get those benefits immediately. Your first VHDL-based project will probably take slightly longer than if you had used your previous design process. Where you really win out is second time around. In order to reduce the time spent on your first project and to ensure that subsequent projects benefit from good VHDL design practices, you need to ensure that your engineers are well trained
I can see how to write abstract behavioural descriptions in VHDL, but how do you describe and simulate the actual hardware?
This is probably the biggest hurdle that many hardware engineers face when moving to VHDL. After all, sometimes we need to be able to describe actual implementation as well as abstract functionality. The way to describe "physical" hardware in VHDL is to write VHDL models of those components. This is supported in VHDL through the use of instantiation. VHDL does not allow you to physically simulate your hardware. You can only simulate a model of that component in a VHDL simulation. Historically, gate-level simulation using VHDL has been notoriously slow. This led to the creation of the 1076.4 working group to provide a mechanism to allow fast gate-level simulation using VHDL. Their effort became known as the VITAL standard. VITAL is not a VHDL issue for you, but an EDA vendor/ASIC supplier issue. A simulator is VITAL compliant if it implements the VITAL package in its kernel (this is faster than simulating the VITAL primitives in the VITAL package). You don’t need to change your VHDL netlist; your ASIC vendor needs to have a VITAL compliant library though, in order for you to take advantage of the simulation speed up. Thus the ASIC vendor’s library elements need to be implemented entirely in VITAL primitives.
I’ve heard that VHDL is very inefficient for FPGAs. Is that true?
How can VHDL be inefficient for FPGA design? It’s a hardware description language. Of course, the problem is with synthesising VHDL to FPGA target technology. You need to use tools that
are designed for targeting FPGA architectures.
Are there any VHDL source code libraries available to save me having to re-invent common code fragments and functions?
There are a few libraries available for most levels of VHDL design. The research library contains very low-level type-and-function packages. The std_logic_1164 package has become an industry standard. Hardly anyone writes a re-usable VHDL component without using this package for the STD_LOGIC and STD_LOGIC_VECTOR type definitions. For libraries of components, have a look in the
comp.lang.vhdl FAQ.
Are freeware / shareware VHDL tools available?
There are a few; generally these are limited in some way (for instance they have no graphical interface, or simulate only certain sizes of model). The VHDL FAQ part 3 has a section on free tools.
Are there any inexpensive VHDL tools available?
Yes, there are one or two. The main FPGA vendors including Altera and Xilinx provide simple toolsets, including a VHDL simulator. These toolsets are normally limited to small devices, and will also have a limit on the number of lines of code you can write; and of course the target technology for synthesis is fixed to a particular manufacture’s chips.
What is Synthesis?
Synthesis is the stage in the design flow which is concerned with translating your VHDL code into gates – and that’s putting it very simply! First of all, the VHDL must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn’t actually produce gates – it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.