tsmc 65nm cmos process
TSMC’s 65nm process is fast becoming the process technology of choice for advanced mobile phone, high definition
digital TV, PC and notebook devices.. Building on this success, TSMC also provides a 55nm half-node process
technology that achieves a better than 20 percent increase in gross die with the same defect density as its 65nm
counterpart. Both process are running in TSMC’s state of the art 12-inch GigaFabs.
The 65/55nm Family
TSMC’s 65nm process offers superior cost-performance benefits, doubling the 90nm process gate density and
boasting a 30 percent speed improvement. The 65nm process supports the foundry segment’s smallest SRAM cell
and reduces power through a multiple-Vt architecture and other process innovations.
The 65nm process family includes general purpose (GP), low power (LP), ultra-low power (ULP), and triple-gate oxide
(LPG) options. Each process supports low, standard, and high Vt options. Operating voltages range from 0.9V to
1.32V. I/O voltages include 1.8V, 2.5V, and 3.3V (5V tolerant). A 5V high voltage DMOS transistor that improves SoC
power management has been added to the 65LP process this year.
The 65nm mixed-signal/RF process is compatible with the logic process and features a complete set of active and
passive devices including resistors, high resistance resistors, MOS varactors, DNW-BJTs, metal fringe capacitors
(MoM), and Metal-Insulator-Metal (MiM) capacitors. The integration of high performance logic functions with reliable
mixed-signal features enhances chip performance and functionality while reducing total material costs. For RF
applications, TSMC offers a thick copper top metal or a logic-compatible top metal layer for high quality inductors.
TSMC also provides a number of models for high precision analog and RF designs including a mis-matching model, a
1/f noise model, a thermal noise model, a CMOS RF model, and a statistical model. SPICE models. TSMC process
design kits (PDKs) provide design infrastructure and flexibility that shorten design cycle time and, ultimately, time-tomarket.
TSMC’s 65nm DRAM memory process is the foundry segment’s most advanced high-density memory process. It
features a cell size reduction of up to 80 percent and provides a significant density advantage over 6T SRAM. It offers
a smaller form factor, lower power consumption, higher bandwidth, and a lower cost. The bit cell features a pass-gate
transistor and a MiM stack as the storage capacitor.
Embedded DRAM is key to empowering bandwidth-hungry networking, game, and high performance graphic
applications. A wide on-chip bus dramatically increases system bandwidth while eliminating costly packaging
configurations. In addition to higher performance and lower costs, a small form factor and low power capability
produce compact devices that are ideal for today’s handheld and miniature consumer electronics applications.
The 55nm process offers a 90 percent linear shrink of the 65nm process. It’s an 81 percent area shrink resulting
in a 23% gross die gain for the same product design . The 55nm process supports a general purpose (GP) core
transistors with an additional ultra high Vt device option. I/O voltages include 1.8V, 2.5V, and 3.3V (5V tolerant).
A 55nm ultra-low power process is ideal for consumer products that require extremely low power consumption.
Lowering the Vcc to 1V for both single port and dual port SRAMs, reduces both active and standby power by more
than 30 percent. The 65ULP process requires one more mask layer than the 65LP process, has achieved the same
D0, yet is available at a similar cost.
TSMC’s design infrastructure is a comprehensive Design EcoSystem that encompasses all critical IC implementation
areas to reduce design barriers and improve first-time silicon success. The EcoSystem includes:
• The foundry segment’s largest and most complete silicon-proven IP and library portfolio.
• An advanced design methodology delivery through reference flows, design for manufacturing, and process design kits.
• Comprehensive design EcoSystem alliance programs covering market-leading EDA, library and IP, and design
The IP/Library Alliance is the industry’s largest and most comprehensive catalog of silicon-verified, production-proven
IP and process-specific libraries. IP cores are validated in TSMC silicon through our CyberShuttleTM prototyping service,
providing the best design experience, easiest design reuse, and fastest integration.
The EDA Alliance, consisting of leading electronic design automation companies, provides a comprehensive set of
process technology files and PDKs that simplify the design process. Selected alliance members work closely with our
design technology services teams to implement TSMC’s design methodology and Reference Flows. Through the Alliance,
EDA companies gain access to TSMC’s technical insights to validate their tools and methodologies. TSMC supports the
industry’s most popular design and verification tools with technology files posted on TSMC-OnlineTM. These tech files are
kept current with optimal accuracy through the cooperation of EDA Alliance members.
The Design Center Alliance (DCA) is a global network of experienced, qualified IC design centers that brings design ideas
from concept to finished product. TSMC’s DCA provides a wide range of IC implementation services. The Alliance’s
combined service capability and capacity dramatically reduce design, manufacturing, and schedule risks.
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