this tutorial to circuit designers who would like to get acquainted with Synopsys design tools. A step by step tutorial approach is adopted. It is the hope of the author that by the end of this tutorial session, the user would have known how to do logic simulation and synthesis.
Those of you who have some basic knowledge of Synopsys tools already may prefer to jump ahead to your desired topic without fearing the loss of continuity. Some topics might appear tedious, but be patient… there’s light at the end of the tunnel. Above all, have fun! Isn’t that what learning is supposed to be?
Synopsys Synthesis Tutorial. Introduction. Design Compiler is the core synthesis engine of Synopsys synthesis product family. It has 2 user interfaces: …
This tutorial basically describes how to use the Synopsys Verilog Compiler Simulator. (vcs) to simulate a Verilog description of a design and how to display …
Synopsys Tutorial: Power Estimation – CVL Wiki
This file will specify to Synopsys and design_vision software what libraries you are using. A sample version of the file is listed below. …
Synopsys Power Analysis Tutorial
This tutorial will provide step by step instructions on how to perform power analysis. We will be using the DECODE design that we previously synthesized to …
Simulation for Power Analysis
This tutorial will provide step by step instructions on how to perform power analysis. We will be using the DECODE design that we previously synthesized to perform power analysis. The following steps of the tutorial assume the first tutorial has been completed. The following files are needed to perform power analysis:
You should already have these files from the pervious tutorial but they have been included above for convenience.
The first step in power analysis is to simulate the synthesized design and gather toggle information. The toggle information that we will be collecting will inform us of when each signal and net in our design chagnes form 1 to 0 or form 0 to 1. Since most power is consumed when a net switches, or toggles, we can then use this information to estimate the power of out design. To gather the toggle information we will follow the following steps.
Simulation Time: We need to know how long we will simulation our design for. During the simulation period the toggle information will be collected. This is typically the length of time the testbench will run for. For example, in our DECODE design, our testbench took 100 ns to run. Therefore, the simulation time that we will want to gather data for is 100 ns.
run.scr: We now need to create a file named run.scr and add the following two lines to the file:
The resulting file should be identical to thid file, run.scr.
Simulation: We can now simulate the design. However, we will not be using vhdldbx as we have done in the past. Instead we will be using vhdlsim to perform our simulation. Simulation is performed by the following commands.
vhdlan -nc decode_gate.vhd
vhdlan -nc decode_tb.vhd
vhdlsim -i run.scr -togfile decode_tc -power_stats CFG_TB
The result of these commands is a file with the name decode_tc. This file contains the toggle information for every net in the design.
sim2dp: Although the toggle file has the information that we need, it is not in the correct format. In order to convert the file into one that we can use, we need to run the following command.
sim2dp -vss decode_tc > decode_sa.scr
This will create a file named decode_sa.scr. This file contains commands that will be used within dc_shell when we perform the power analysis. Note that you must download sim2dp as it is not installed on the system.
sim.scr: This script file can be used to automatically run the appropriate commands needed for simulating our design for power analysis. Note that this script is run directly forom your shell and thus the file must have executable permissions.
The actual power analysis will be performed using dc_shell. The first step of power analysis is to run dc_shell. The following provides the remaining steps with information regarding each step.
Read in our synthesized design: We need to read in our synthesized design. This is where the file decode_gate.db is very important. Because this file is in the format directly readable by dc_shell, it is very quick to read this file. If we were to use the decode_gate.vhd file instead, dc_shell would actaully have to compile the design again, which we do not want to do. Therefore, we can read in the design by using the following command.
Operating Conditions: Without going into too much detail, the following commands need to be used to provide Synopsys with information regarding our operating conditions.
set_operating_conditions -library “lsi_10k” “WCCOM”
set_wire_load “10×10” -library “lsi_10k”
set_driving_cell -cell AN2P -library lsi_10k all_inputs()
Create clock: If there is a clock in our design we must create a clock. The command works by creating a clock that will be used in power analysis. In the testbench of our design, we would have simulated a clock with a given frequency. Therefore, we will need to create a similar clock within dc_shell. This is done by the following command.
create_clock find(port, “clk”) -period 5
This will create a simulated clock attached to the port named “clk” with a period of 5 ns.
If we do not have a clock then this command will fail, however it is very easy to create a generic script file and including this command will not create any problems.
Switching activity: We will now use the information gathered from simulation. By including the decode_sa.scr file, dc_shell will annotate each net in the design with the information we previously gathered. This is performed using the following command.
Power Analysis: We are now ready to perform the actual power analysis. This is done with the following command.
report_power -analysis_effort high
At the end of the output from this command, dc_shell will report the power used by our design.
power.scr: This script contains all of the dc_shell commands needed to perform power analysis. As before, the script can be executed by entering the following command form within dc_shell.
Congratulations. You have successfully completed the power analysis of the DECODE design that was previous created.