SYMBOLIC EXTRACTION FOR ESTIMATING ANALOG LAYOUT PARASITICS IN LAYOUT AWARE SYNTHESIS
This paper presents a new layout parasitic extraction paradigm, symbolic extraction, for use in layout-aware analog synthesis methodologies. Unlike traditional post-layout extraction, symbolic extraction extracts layout parasitics in symbolic form from parameterized layouts. As a result, parasitic values can be calculated directly from given circuit and layout parameters. In layout-aware circuit synthesis process, tasks of time-consuming layout re-generation and reextraction can be replaced by this fast parasitics calculation step. In the paper, we discuss how to integrate symbolic extraction into the existing analog design flow and how symbolic extraction can be implemented.
One critical problem in analog integrated circuit design is layout-induced parasitics. Layout parasitics can have significant effects on design performance, especially for high-frequency circuits. In an experiment for impact of parasitics , design performance can be shifted as high as 90% if parasitics are not considered. In order to take layout-induced effects into account in analog design process and automate the redesign loops, layout-in-the-loop synthesis methodologies [2, 3] have been proposed, as illustrated in Fig. 1(a). In these methodologies, layout generation and parasitic extraction steps are required in that we need to know the performance degradation induced by the layout. The results of extracted net-lists are then used to guide synthesis tools for the next circuit sizing loop. Although layout generation and extraction steps are very important to the methodologies, they are very time-consuming.
Novel methodologies toward solving slow layout generation and extraction in layout-aware synthesis flow have been proposed. In the approach of using Module Characterization Table (or MCT, a type of lookup tables) to estimate parasitic values has been proposed. However, one problem of this approach is that the size of an MCT can grow exponentially, especially when there are many variables for the input column. Another problem is that the routing is oversimplified. The use of routing boxes, that each of them consists of a horizontal and several vertical segments, is not the case in general, especially for high-performance analog circuits. Proposed by the same research group at the University of Cincinnati, the pre-layout extraction approach uses a high-level language, MSL, to generate extracted net-lists from given circuit parameters without generating a concrete layout . However, there are disadvantages for this methodology. One drawback is that it is not simple to define extraction sections in MSL. To specify rules and variables in an extraction section, designers first have to analyze the module generator and have to have a picture in mind in advance for what the final extracted net-list will look like. Then they have to manually define the connections of each active and passive element by using the language. After that, designers assign the associated variables or values to those elements. The procedures above are like coding parasitic extractors manually for each module. In addition, each module generator must have at least one version of its own extraction sections for the purpose of different levels of accuracy. For large modules, therefore, using the language to define the extraction sections would be a very tedious work. Our idea is similar to pre-layout extraction and the MCT approach because no detailed layout is generated in order to attain extracted net-lists during layout-inclusive synthesis process. On the other hand, our approach has the following distinctions. (1) Extracted net-lists in our