Sources of Static Phase Offset
A significant source of timing errors is device mismatch and asymmetries in circuits and layout. These errors are not fundamental limitations, since device mismatch can be reduced with larger devices and layout asymmetries can be reduced with multiple fabrication trials, but they do present practical limitations. In all real designs, both transistor sizes and design time are limited.
In both a DLL and a PLL, the control loop feedback clock increases the load on one of the output phases. To maintain symmetry, dummy loads are used to balance loading on all phases, but this requires additional area and power. DLLs have further circuit asymmetries because of delay elements required at the ends to the delay line. The buffers at the end of the DLL only cost area and power, but those at the beginning will contribute additional jitter, as described in Section 3.4, because the reference clock edge must traverse through these buffers before going through the delay line. Care must be taken to ensure changes made to improve matching do not create additional jitter. The layout of multi-phase clock generators, especially those with large numbers of clocks is difficult because of matching and the resulting asymmetries are a significant source of static phase offsets. First-order matching of layout capacitance is straightforward, but matching second-order effects, such as coupling between active signals is more challenging. Extraction tools can produce detailed models of the parasitic capacitances, but the effect of coupling capacitances depends on the edge rate of the coupling signals, which can change over process corners. Static phase offsets are also caused by synchronous supply noise at the same frequency as the clock generator. To understand why this happens, consider Figure 3.4 depicting three clock waveforms and the absolute value of their noise sensitivity functions (NSF) as described by Hajimiri and Lee . The NSF of a circuit represents the delay sensitivity of the circuit (in this case, a clock buffer) to power supply noise as a function of time. The value of the NSF is zero when the buffer output is not in transition and non-zero when the output transitions. Noise will only affect the buffer delay when the NSF of that buffer is non-zero.