Every CMOS VLSI chip that is produced needs to be tested to ensure it was manufactured correctly. Test and possible debug has always been a challenging task that requires specialized hardware “testers.” Furthermore, the rapid scaling of chip performance is making test increasingly difficult. Until recently, testers were able to leverage process technologies with intrinsic performance greater than CMOS to obtain sufficient timing capabilities to accurately test CMOS parts. However, because the performance of CMOS technology has scaled faster than the performance of other process technologies, using non-CMOS process technologies to build testers suitable for testing modern VLSI parts is becoming more difficult. CMOS process scaling has not only enabled faster clock rates, but also increased chip functionality. As technology scales, more complex designs can be integrated on a chip to improve performance, because on-chip communication is vastly faster than external interconnects. However, an undesirable effect of integration is a reduction in the observability of the system, and, as a result it is more difficult and costly to test and debug a part. Building the tester pin electronics in CMOS and in some cases, even integrating the pin electronics into production parts can address both performance and observability and lead to easier test and debug. This thesis addresses key issues in building high-speed testers in CMOS.

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