pass transistor and nmos pmos

Pass-transistor logic, in the present discussion, consists of a type of metal/oxide-or-insulator/silicon-or -semiconductor (MOS) logic integrated in integrated circuits (IC’s). MOS transistors are used as switches. An n-channel (NMOS or nmos) transistor is turned on by application of a positive input voltage, approximately equal to the positive supply voltage, to the nmos gate terminal, and is preferably turned off by connecting the nmos gate to a voltage approximately the value of the negative supply terminal voltage. A p-channel (PMOS or pmos) device is turned on by connecting the pmos gate to a voltage approximately the value of the negative supply, while the pmos is preferably turned off by connecting the pmos gate to a voltage approximately the value of the positive supply voltage.
The problem with pass-transistor logic is that the pass-transistors, which function in a sense, ideally, as series switches in a logic-signal, signal path, for the logic input which connects to a source/drain diffusion, also function as source followers with respect to the gate input of the pass-transistor. Thus, for a simple pass-transistor gate, an nmos drain will be one input terminal, the nmos gate will be a second input terminal, and the nmos source will be the output terminal. Now, if both the drain voltage is high and the gate voltage is high, then the output, source voltage will be high. High means approximately equal to the positive logic-level voltage, usually the positive supply voltage. But for each such AND gate which a logic signal is required to propagate, by way of a series of gate-input-connections, the logic gate output voltage will be one nmos-transistors gate-source threshold voltage lower than the nmos-gate-terminal logic gate input voltage. Similarly, a pmos AND gate would suffer from an upward level-shifting of the output voltage with respect to the pmos-gate terminal input voltage.
Thus, it is necessary after each pass-transistor logic gate, or after each so-many logic gates, to perform a logic-level “restoration”. The need for restoration is due to the fact that the “weak logic state 1”, a logical 1 having a dc level one threshold voltage below the positve rail, will cause DC voltage leakage if the weak logic state 1 output will then be used as an input to another, following, cmos gate, since the input PMOS of a cmos gate will then not be completely turned off. In addition if the weak logic state 1 will be used as a gate signal to another NMOS pass transistor, the NMOS pass transistor output will then be two threshold-voltage drops lower than the positive rail. This is the problem discussed in the previous paragraph with respect to AND gate use of the pass transistors. In complementary MOS (CMOS or cmos) logic, the output of the basic pass-transistor logic gate is connected to a cmos inverter input. The cmos inverter output swing is from supply-rail to supply-rail. Therefore, the logic level of the inverter output logic signal has been restored to the ideal logic-level values. The restoration is due to the PMOS latch before the output inverter that is used only as a buffer. This latch is not always used in CPL, which is discussed below. The “original” CPL, to be discussed below does not have this PMOS latch and hence suffers from leakage at the inverter, due to the reason mentioned in reference 4. The inversion due to the cmos inverter must be taken into account in the system logic design. The easiest way to accommodate the additional logic-signal logical inversion due to the added inverter, is to include the inverter in the unit pass-gate design, with the resulting pass-transistor logic gate then including both the correct logic function terminal definition, and including logic level restoration. The FRCPG logic family of the present invention incorporates these features.
nMOS: negatively doped silicon, rich in electrons.
pMOS: positively doped silicon, rich in holes (the DUAL of electrons).
For electrical reasons, it turns out that pMOS transistors are great at transmitting a logic 1 voltage without signal loss, but the same cannot be said about logic 0 voltages. Having 0 V at one side of a conducting pMOS transistor yields a voltage at the other side somewhat higher than 0 V. NMOS transistors have a -complementary problem: they are great at passing logic 0 but awful at passing logic 1.
As you may guess, the best possible transmission behavior can be -obtained by combining both kinds of transistors. This yields the CMOS transmission gate or pass gate.