mixed signal development tool

mixed signal designs, there has to be a mix of design flow, for higher level system description and verification AMS , block level with spice (analog) and rtl(digital) based and full-chip level fast spice.there always have to have possibility of backannotation and postLO(extracted) info to be inserted flexibly and design flow should be able to support multiple views (hdl,schem,ext etc) of design flows.
With AMS environment it becomes quite convenient to manage and change the verification flow and not to mention system evaluation.
Mentor has ADvanceMS (AMS),eldo(spice type) and ADiT (fast spice) and all of them are tightly integrated and well suited for a typical Mixed signal flow.
Cadence has AMSdesigner(AMS),spectre(spice type) and Ultra sim (fast spice)
synopsys has DiscoveryAMS (AMS),HSPICE (spice level) and HSIM and nanosim(fast spice).
Magma has Finesim (spice) and Finesim-pro(fast spice)
generally it is possible to mix the tools as well.
Each of the design has its own peculiarities and so chip-level verification strategy is different for various designs.You have to foresee the issues while deciding upon the way to take and setup your verification flow as wrong choices cost time and tedious workarounds.
Many teams delay full chip verification to last stage of design and this could be costly (especially for bigger designs).
AMS design entry does not start at transistor-level/layout/RTL, which is already implementation level, but should start at system-level. Especially for AMS chip-level design and verification, having system-level representations and AMS behavioral models is very valuable to explore architecture topologies and implementation aspects as part of the design phase, and these reference designs and testbenches can be reused in the verification phase of the project. At implementation level, languages like Verilog-AMS and VHDL-AMS are suitable for AMS behavioral modeling and these languages are supported by almost all commercial EDA tools. For functional modeling, Mathematical tools and data-flow-oriented tools are used to design procedural functions and algorithms, but this is not always suitable for (AMS) architecture studies. Especially for this AMS architecture-level work, the current AMS design flows are not mature and clearly not “state-of-the-art”, although there are languages out there like SystemC and the upcoming SystemC AMS extensions which target digital HW/SW + AMS co-design. SystemC is already supported by most of the EDA vendors; the AMS extensions are being standardized right now and we have to see how fast the EDA vendors will embrace this new standard. Commercial AMS design flows should address the system-level requirements to be able to design and validate complex mixed-signal chips.