This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds;sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds;sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-di®erential rail-to-rail ampli¯ers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage ampli¯er with a bulk-driven input pair while showing no bandwidth degradation when compared to ampli¯er architectures with similar biasing. The low voltage design techniques are extended to switching and sampling circuits. A 10-bit digital to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are designed and fabricated in a 0:35¹m dual-well CMOS process to prove the developed design methods, architectures, and techniques. The 10-bit DAC operates at 1MSPS with near rail-to-rail di®erential output operation with a 700mV supply voltage. This supply voltage, which is 150mV lower than the VT +2Vds;sat limit, is attained by using a bulk driven threshold voltage lowering technique. The ADC design is a fully-di®erential pipelined 10-bit converter that operates at 500kSPS with a full scale input range equal to the supply voltage and can operate at supply voltages as low as 650mV, 200mV below the VT + 2Vds;sat limit. The design methods and architectures can be used in advanced processes to maintain gain and minimize supply voltage. These designs show a minimum supply improvement over previously published designs and prove the e±cacy of the design architectures and techniques presented in this dissertation.
The trend in integrated circuit fabrication since its inception has been a move toward decreased geometry sizes to increase circuit capacity and speed and reduce power consumption. As transistor sizes decrease, the circuit functionality of a given area of substrate can be increased. Smaller device sizes also yield lower parasitic capacitance which increases speed and decreases power consumption. As process geometries decrease, operating voltages must be scaled down due to increased electric ¯elds and reduced breakdown voltages caused by higher doping pro¯les. Decreased operating voltages facilitate lower power consumption which is increasingly important as circuit complexity increases. However, analog circuit design becomes more difficult as supply voltages decrease.
Advanced CMOS processes show a nearly linear correlation between line width and maximum supply voltage. However, the threshold voltage, VT , of transistors decreases at a much lower rate as shown in Figure 1.1. The di®erence between the supply voltage and the VT determines the input voltage range of a transistor or the operational input headroom of the process. This also de¯nes the voltage range available for signals and biasing architectures. The maximum input headroom value has dropped from 4.2V with 0:5¹m processes to less than 0.7V with 0:09¹m processes, and will continue to decrease with advanced processes. As supply voltages lower than the process maximum are chosen to reduce system power the operational input headroom is decreased further.
The push toward more complex integrated systems requires lower power and thus lower supply voltages. The minimum supply limit for analog circuits which operate in the active region can be determined by the analysis of a simple circuit with a single p{channel and n{channel transistor. The p- channel transistor must be able to drive the gate of the n-channel transistor while remaining in the active region to propagate a bias current. This requires the drain to source voltage of the p-channel transistor to be greater than Vds;sat, the drain to source saturation voltage.
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