hyper transport technology

HyperTransport is a high-speed, point-to-point, 32-bit technology for data transfer within the integrated circuits ( IC s) in computers and other devices. The technology allows data throughput in excess of 12.8 gigabytes per second (GB/sec). HyperTransport was developed by AMD in cooperation with several other companies, and is a trademark of the HyperTransport Consortium.
Computers using HyperTransport are characterized by low latency , compatibility with most operating system s, low pin count, scalability , and extensibility to advanced bus architectures. HyperTransport will work with a wide variety of input-output (I/O) devices, and a single channel can accommodate multiple devices.
HyperTransport is aimed at applications that require greater bandwidth than other current technologies allow. HyperTransport has obvious advantages in applications such as high-end animation programs, simulation programs, robot control, medical devices, and virtual reality . Some engineers envision the eventual use of this technology in general consumer appliances and electronic devices.
HyperTransport technology is a high speed, high performance chip-to-chip interconnect primarily intended for use on a system board within distances of up to 24 inches.
The specification has been proposed by Advanced Micro Devices and is promoted by the Hyper transport Consortium. Hyper Transport technology is designed to transfer data at 6.4 Gigabytes per second.
The Hyper Transport Consortium is in charge of promoting and developing HyperTransport technology.
HyperTransport is packet-based, with each packet always consisting of a set of 32-bit words, regardless of the physical width of the connection. The first word in a packet is always a command word. If a packet contains an address, then the last 8 bits of the command word are chained with the next 32-bit word in order to make a 40-bit address. An additional 32-bit control packet is allowed to be prepended when 64-bit addressing is required. The remaining 32-bit words in a packet are the data payload. Transfers are always padded to a multiple of 32 bits, regardless of their actual length.
HyperTransport is a CPU to I/O and CPU to CPU bus design.
HyperTransport is an open standard which has been incorporated into AMD’s Opteron and Athlon64 64-bit x86 processors, Transmeta’s Efficeon x86 processor, Broadcom’s BCM1250 64-bit MIPS processor, and PMC-Sierra’s RM9000 64-bit MIPS processor family.
HyperTransport utilizes a packet-based protocol to maximize flexibility while minimizing the number of data paths required for command and control.
HyperTransport is a point-to-point architecture instead of a shared architecture like PCI or PCI-X.
HyperTransport is built upon 1.2 volt Low Voltage Differential Signaling (LVDS) to reduce signal noise.