HiPEAC Workshop on Reconfigurable Computing 2010
4th HiPEAC Workshop on Reconfigurable Computing
January 23, 2010
The HiPEAC Workshop on Reconfigurable Computing WRC’10 provides a forum for researchers active in domains within the reconfigurable computing area. Its main focus is on reconfigurable architectures, tools that facilitate such architectures, and applications tailored for reconfigurable platforms. The workshop intends to bring together both hardware designers and software developers that make extensive use of reconfigurable computing. Moreover, it aims at enabling scientific discussions regarding future challenging issues.
This workshop is co-located with and followed by HiPEAC’10 (2010 International Conference on High Performance Embedded Architectures & Compilers) in Pisa, Italy .
The topics of interest include, but are not limited to:
Novel architectures (logic blocks, interconnects, I/O);
Reconfigurable fabrics combined with dedicated system blocks (DSP, processors, memory etc.);
Memory issues: adaptivity, coherence, latency tolerance, etc.;
Multicore support, resource sharing support, etc.;
Low power reconfigurable architectures;
Networks on Chip tailored for reconfigurable architectures;
Dynamic and run-time reconfiguration;
Defect and Fault tolerance.
Reconfigurable Tools and Technologies:
System level design and HW/SW co-design;
Static and dynamic power efficiency;
Modeling, optimization, technology mapping and design verification;
Design and debug of reconfigurable systems;
Testing, verification and benchmarking;
Dedicated compilers and high-level languages;
Operating system support for reconfigurability;
Impact of reconfigurable hardware on real-time performance.
Reconfigurable Applications and Algorithms:
Adaptive and bio inspired applications;
Application domain specific, e.g. multimedia, bioinformatics, cryptography and more;
High-performance, high reliability and/or power efficient application acceleration;