Ground Bounce in pcb layout

As digital devices become faster, their output switching times decrease. Faster switching times cause
higher transient currents in outputs as they discharge load capacitances. These higher currents, which are
generated when multiple outputs of a device switch simultaneously from a logic high to a logic low, can
cause a board-level phenomenon known as Ground Bounce. Many factors contribute to ground bounce.
Therefore, no standard test method predicts ground bounce magnitude for all possible PCB environments.
Determine each condition and each device’s relative contributions to ground bounce by testing the device
under these conditions. Load capacitance, socket inductance, and the number of switching outputs are the
predominant conditions that influence the magnitude of ground bounce in programmable logic devices.
Guidelines reduce ground bounce:
• Use wide, short traces between the via and capacitor pads, or place the via adjacent to the capacitor
• Traces stretching from power pins to a power plane (or island, or a decoupling capacitor) must be
as wide and as short as possible. This reduces series inductance, and therefore, reduces transient
voltage drops from the power plane to the power pin. Thus, reducing the possibility of ground
• Connect each ground pin or via to the ground plane individually. A daisy chain connection to the
ground pins shares the ground path, which increases the return current loop and thus inductance.
• Add the recommended decoupling capacitors for as many VCC/GND pairs as possible.
• Place the decoupling capacitors as close as possible to the power and ground pins of the device.
• Add external buffers at the output of a counter to minimize the loading on silicon device pins.
• Configure the unused I/O pin as an output pin and then drive the output low. This configuration
acts as a virtual ground. Connect this low driving output pin to GNDINT and/or the boards ground
• Configure the unused I/O pins as output, and drive high to prevent VCC sag.
• Turn on the slow slew rate logic option when speed is not critical.
• Limit load capacitance by buffering loads with an external device, such as the 74244 IC bus driver,
or by reducing the number of devices that drive the bus.
• Eliminate sockets whenever possible.
• Reduce the number of outputs that can switch simultaneously and/or distribute them evenly
throughout the device.
• Move switching outputs close to a package ground pin.
• Create a programmable ground next to switching pins.
• Eliminate pull-up resistors or use pull-down resistors.
• Use multi-layer PCBs that provide separate VCC and ground planes to utilize the intrinsic
capacitance of GND-VCC plane.
• Add 10 to 30 ohm resistors in series to each of the switching outputs to limit the current flow into
each of the outputs.
• Create synchronous designs that will not be affected by momentarily switching pins.
• Assign I/O pins to minimize local bunching of output pins.
• Place the power and ground pins next to each other. The total inductance will be reduced by mutual
inductance, since current flows in opposite directions in power and ground pins.