GPS RFIC is a low cost CMOS low-IF GPS receiver. It covers all RF circuitry needed for a robust, high performing GPS receiver. It includes on-chip low noise LNA, a mixer down converting and analog baseband supporting 2/3 bits signed magnitiude output. The chip integrates a fractional-N PLL with on-chip XO supporting all GSM crystals from 10 to 52 MHz. Supported with a powerful power management unit guaranteeing operation at the lowest possible power, and based on 65nm technology, our GPS is the most optimum solution in the market for cellular devices.
RF front-end GPS single-chip receiver
65nm CMOS Technology
Integrates all RF circuitry including: on-chip LNA, AGC, ADC, and Fractional-N PLL synthesizer
Optimized for cellular and mobile handsets
Supports all GSM crystals (10-52) MHz
State-of-the-art design to support location-based services
Technical Specifications
RMS phase error < 3 degrees
3.5GHz VCO with low Kvco variations
MMD with -155dBc/Hz @ 100KHz offset
CP noise < 1.8pA/sqrt(Hz) @ 75uA CP current
XO with phase noise < -125dBc/Hz @ 1MHz offset
Supply regulators included
Current consumption < 22mA
-155 dBm sensitivity level with on-chip LNA
NF < 2.5dB
Optional off-chip SAW filter for additional interferer rejection
Optional external LNA can be used to support different board designs

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