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floor planing of chip


Due to increase in number of components on a chip, floorplanning is important step in Very Large Scale Integration physical design to ensure quality of design. Various iterative approaches have been suggested to carryout floorplanning in Electronic Design Automation tools. Iterative approaches can produce good results but they are slower. In this thesis, we have taken bottom-up, recursive approach to floorplanning. We have also suggested efficient exhaustive search procedure for placing two, three or four rectangular blocks in a floorplan. A rectangular block can either be hard or soft and resultant floorplan can either be slicing or non-slicing. Further more exhaustive search procedure can also be extended for five or more rectangular blocks. We have developed two algorithms, which fall in class of constructive approaches rather than class of iterative approaches. These algorithms use exhaustive search procedure, works in bottom-up constructive manner and they are recursive in nature. These algorithms are very fast compared to other search algorithms and also producing promising results. Complexity of these algorithms is O(n). Experiments results with MCNC circuits indicate that area utilization of about 85-99% can be achieved in very less time then iterative algorithms.