Fast Accurate Routing Delay Estimation

We propose in this paper a novel approach for speeding timing closure. We focus on the problem of accurate post-routing delay estimation from a given placement. Post-routing delays differ from placement delays due to factors such as net topology, layer assignment and congestion. Fundamental to our approach is utilizing an existing base design to predict future designs. We present four wire-delay estimation techniques based on: delay fitting, Steineraware delay fitting, Steiner-aware RC sampling, and scaled Steineraware RC sampling. We apply our techniques to several designs, and using an industrial flow, we demonstrate that it is possible to estimate the routing delays with an average estimation error of 16% on benchmark circuits. These results are of practical value, and improve on the state-of-the-art industrial estimation capabilities.
The objective of a priori wirelength estimation is to predict the length of a net route before the computationally intensive routing stage. The wirelengths are used to compute delays, which are utilized to speed up physical synthesis and to reduce the number of required design iterations. Several wirelength estimation techniques have been investigated. The main hypothesis motivating previous work in wirelength estimation is that wirelength correlates well with post-route delay. However, post-route delays differ from placement estimates mainly due to net topology, routing congestion and layer assignment. Congestion occurs due to blockages and fi- nite routing resources, which changes the topology of nets to avoid congestion. Layer assignment can significantly change delay. For example, a net of estimated length of 100 mm will have a delay of 0.9 ps if routed in the fourth metal layer in a typical 90 nm process, but it will have a delay of 1.3 ps if routed in the first metal layer. The layer choice results in a delay difference of 44%.
The problem we address in this paper is a priori wire delay estimation where the estimation occurs after placement but prior to routing. Our underlying approach is based on characterizing a known design, referred to as the base design, to predict delays for a design variant or other designs that utilize the same router. Our estimation approach captures empirically the router characteristics as encountered in the base design and this empirical information is used to estimate the delays of other designs. Our approach is practical as designers typically use the same router in either designing a next-generation product based on one with similar function (a design variant), or designing a new integrated circuit using the same design technology (different design, same technology). We present in this paper four techniques to estimate routing delays. We demonstrate the results of applying these techniques to estimate the delays of design variants and completely different designs than a base case. We highlight our contributions:  We propose four delay estimators that vary in complexity and in estimation capabilities. These estimators incorporate many factors from the base design to determine the final pin-to-pin routing delays. These factors include net degree, Steiner wirelength, and the general impact of topology and congestion.
 Our estimators empirically capture the routing characteristics
of a given router and thus the estimation results are likely to
occur when the same router is utilized. Thus, the applicability of our approach is ideal in an industrial setting where the
same router is used across different designs.
 Our estimators use lookup tables, therefore quickly providing estimation results. The estimation runtime is essentially
proportional to the number of the pin-to-pin paths in a design. Our approach is scalable and adaptable to very large
 Utilizing an industrial design flow, we validate the accuracy
of our delay estimates against the actual detailed routes. Our
experimental results indicate that we are able to achieve an
average 16% estimation error across a number of different
designs and design variants.

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