ESD Protection Methods

ESD protection methods for ICs can be considered to be either external or internal
chip protection schemes. External ESD protection methods include storing chips in
shielded containers and handling them in static free environments. On the other
hand, internal methods require integration of on-chip protection devices, which are
intended to provide an explicitly robust path for ESD strikes between any pair of pins
. The protection circuit generally discharges the ESD strike by providing a low
impedance path to ground, thereby shunting most, if not all of the transient away
Figure : A Simple ESD protection circuit.
from the sensitive core circuit(s). The protection circuit should also clamp the pad
voltage to a sufficiently low level during the duration of the ESD event.
A typical on-chip protection circuit is placed between the signal pin and the main
circuit, as shown in Figure 2.1 [30]. In this case, the diodes shunt excessive positive or
negative voltage applied to the signal pin towards GND or Vcc, respectively, diverting
the ESD strike from reaching the main circuit. The complexity of the protection
system increases with the number of pins to be protected. It should be noted that
an ESD protection circuit need not necessarily be based on diodes; depending on
the available technology, it may be composed of various devices such as thick field
oxide (TFO) clamps, silicon controlled rectifiers (SCRs), Medium-Voltage Triggered
SCRs (MVTSCRs), spark-gaps, or transistors . TFOs and SCRs fall under the
category of breakdown based clamps. A TFO clamp consists of an NMOS transistor
(used in grounded gate configuration) with a TFO gate which is tied to the drain.
The trigger NMOS is usually a thin field oxide device and hence its drain needs to be
protected using a resistor. SCRs do not have such triggering mechanisms and hence
require higher voltages for triggering. Also SCRs take a finite time (?1ns) to latch
up which makes them too slow for many applications . MVTSCRs are formed by
adding a bridging N+ region between the N-well and the P-epitaxial layer. As the
N+/P-epi junction has a lower breakdown voltage than the N-well/P-epi junction,
the MVTSCR has a lower triggering voltage as compared to the normal SCR .
Ideally the protection system must not affect the input/output signal under normal
operating conditions. However, the ESD protection devices present unwanted para-
sitic capacitances and resistances to the signal path, which can have an adverse effect
on the performance of high speed and RF circuits. In particular, at RF frequencies,
the parasitics associated with the ESD structures can lead to impedance mismatches,
causing reflection of signals and degraded power transfer between signal pin and the
core circuit.
Historically, the design of ESD protection circuits in RF systems has been an empirical,
trial and error process in which several variations of a particular circuit are
laid out, processed, packaged and tested on a pass/fail basis. This approach is time
consuming and must be repeated as technologies evolve. However, advancements in
CAD software and better device modeling have made the simulation of ESD events
in integrated circuit designs practical. Such simulations can help predict a circuit?s
current-voltage response to an ESD stress event, allowing designers to evaluate the capabilities
of protection circuits without costly and time-consuming fabrication, packaging,
and testing cycles.