Emulation in asic design
Emulation is replicating the ASIC design using generally the FPGA’s, its a real piece of hardware. Simulation on the other hand is on the RTL, w/o real hardware. Emulation is useful for developing the software/firmware and even testing the hardware. However many companies use the Emulation to validate the Hardware before ASIC tapeout. Having said that Emulation generally has to be finished before the ASIC is taped-out, so that the desired HW testing is finished before tapeout. I have seen many companies use emulation for Software testing rather than hardware testing.
Emulation is similar to building a FPGA prototype, although commercial emulation offerings generally have better debugging capabilities (not unlike those you’d find in a simulator, with waveform viewing, breakpoints etc.) than is possible with an FPGA.
The classical application of an emulator is to allow you to plug the emulated device into the PCB or system that it’s going to be a part of though personally I’ve never seen it done in practice – most people seem to use emulation more as a fast simulator. Emulators tend to work much more quickly than simulators, but generally not real-time, so if your application depends on real-time interfaces (like video, audio and so on) then it’s necessary to have dedicated hardware to stream data (in or out) at the rate that the emulator is running at, these issues can be a major obstacle to getting useful results from an emulator.
In general I feel that modern verification techniques such as coverage driven directed random stimulus and some of the formal techniques have rendered emulation less useful than it once was. Emulation tends to get squeezed because you really need the complete RTL finished before you can start emulating and often, if there’s been any slip in the plan there’s tremendous pressure to tape-out before you really see results from emulation.
If you accept that reality then perhaps emulation is really most useful as a debugging tool – when the silicon’s come back and it isn’t working properly, then if you have a working emulation (and you had the FAB cycle to get it working) then it’s much easier to debug design issues on the emulator than on the silicon. Emulation can be useful as a way to get hardware in the hands of a software team early, but here the requirement is usually to get multiple copies of the hardware – one for each software engineer – and an FPGA rig is probably going to be much more economic than an emulator.
I’m skeptical of the value of emulation and given that it is a relatively expensive option (you’ll need dedicated engineers as well as the expensive emulation hardware and software to drive it) I think it might be better to redirect that money towards early system level modeling, properly structured verification and additional workstations and simulation licenses.
Emulation is necessarily one of the steps in verification of ASIC. In the ASIC design one will typically perform simulation of HDL while the developing various bocks or while integrating various IPs. Once RTL is verfied using simulations and various IPs are integrated you will need an emulation platform. For emulation various FPGAs or products based on FPGAs are used. FPGAs allow reconfigurabilty and also the design can run several magnitudes faster than simulation, this enables verification team to run long test sequences quickly and also allows configuration of different features.
Type and count of FPGA devices determine number gates of ASIC to be emulated. Apart from hardware FPGAs, the software which partitions the ASIC to various FPGAs plays big role in determining speed of emualtion.
Apart form verification of ASIC emulation helps in development of embedded software including real time operating systems.
Emulation is implementing parts of a system on a platform other than the actual one. One concrete example is emulation of a processor before the actual processor hardware is available so software developers can use the emulated part to develop their code while the asic is being implemented. There is also a more restricted use of emulation which is the use of a prototype during the actual development of the ASIC for testing purposes. This use usually replaces simulation and is much faster than simulation. Emulation can start as early as just after completion of the system models for the ASIC. The models can be executed in a different platform than the ASIC hardware. Emulation for the purposes of the ASIC usually comes during verification stage where all the RTL design is done and system test/verification can start. Emulation can be accomplished by FPGA prototyping, Palladium or Eve type hardware where the RTL is either mapped to FPGA hardware or to some form of high speed cpus targetted for RTL simulation.