dual edge triggered sense amplifier flip flops-thesis

Dual-Edge Triggered Pulsed Flip-Flop With High Performance And
High Soft-Error Tolerance
Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the whole synchronous circuit. In this thesis, a dual-edge triggered flip-flop with high performance and high soft-error tolerance is designed. Pulse-triggered flip-flops employ time borrowing across cycle boundaries which results in zero or negative setup time. Moreover, the pulse generator can be shared among many flip-flops to reduce the power dissipation and chip area. Pulse generator provides a narrow window to the latching stage during which the flip-flop is in the transparent mode. By reducing this pulse width, the setup time and hold time of the flip-flop are reduced. In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed. With the increasing of the transistor densities and the technology scaling, the circuits are more and more sensitive to the externally induced phenomena called soft-error. The occurrence of this kind of faults will affect the integrity of the data, and the flip-flop can cause malfunction. It is critical to design integrated circuit with high soft-error tolerance. Comparing to other flip-flops in the latest publications, the Clock-to-Q delay, setup time , hold time and power consumption of this flip-flop are all smaller and the critical charge of the flip-flop is increased significantly resulting in much better hardness against alpha particle hits. Moreover, a scan chain algorithm used to test faults in combinational logic is proposed using the dual-edge triggered flip-flop along with the scan control signal incorporation in this thesis. The result of the simulation demonstrates that this dual-edge triggered flip-flop is a viable means to improve design performance and to ease the strict and tight timing budget.

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