Design Considerations in Deep Submicron CMOS Technologies-free thesis

Mixed Analog Digital Design Considerations in Deep Submicron CMOS Technologies
Higher speed and higher density are the main thrusts of CMOS technology and are achieved by device miniaturization. In deep submicron geometries, the supply voltage is scaled down to prevent reliability hazards such as oxide breakdown and hot carrier effects and also to reduce energy per operation of digital circuits. Lowering the supply voltage directly reduces the signal swing, which in turn makes the design of high-speed wide dynamic range mixed-signal SC circuits a challenge. It is also desirable to implement SC circuits in a standard digital CMOS process, where double-poly capacitors are not available, because the driving forces behind the CMOS technologies are DRAMs and microprocessors which do not require linear capacitors.
CMOS Scaling The scaling of CMOS technology is achieved by reducing the dimensions of MOSFET transistors by a factor of ( ). The original Constant Electric-field (CE) scaling law proposed involved supply voltage scaling as well as scaling all the device dimensions to preserve the same electric-field in the scaled-down device. A constant electric-field in the substrate is obtained by increasing device-well doping concentrations in the smaller devices. The CE scaling scheme improves the device density by , reduces the gate delay by , and lowers power dissipation by thus maintaining a constant power density

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