Comparison between chip floor planning and block-level floor planning

comparison to chip floorplanning, block-level floorplanning has the following
similarities and differences:
• At the block level there may be thousands of cells; at the chip level the
number is usually less than 20
• Port handling is similar, although there may be many more ports
• The pins in a block can number in the hundreds of thousands, and the connectivity
is much more complex than at the chip level
• If the process has more than three layers of metal, the floorplan may not have
channels at all—the plan will look like a sea of cells
• In the case where there are imported or hard cores, the floorplanner will
optimize their placement among the rest of the logic.