CMOS RF RMS Detector for Built in Testing of Wireless Transceivers

A CMOS RF RMS detector is introduced. It generates a DC proportional to the RMS voltage amplitude of an RF signal. Its high input impedance and small silicon area make it suitable for the built-in testing (BIT) of critical RF blocks of a transceiver such as a Low Noise Amplifier (LNA) and Power Amplifier (PA) without affecting their performance and with minimum area overhead. The use of this structure in the fault detection and diagnosis of a wireless transceiver is described and illustrated with an example. The transistor-level implementation of the proposed circuit is discussed in detail. Post-layout simulation results using CMOS 0.35┬Ám technology show that this testing device is able to perform an RF to DC conversion at 2.4GHz in a dynamic range of 20dB using an area of only 0.0135mm and presenting an equivalent input capacitance of 22.5fF.
The wireless communications market is a major driving force of the semiconductor industry. Modern integrated transceivers are complex systems that involve RF, analog and mixed-signal circuits; as a result, their testing is complicated, expensive and has become a significant portion of the final product cost. Two of the most important challenges that test engineering faces to make a wireless product competitive are (1) to accelerate the time-to-market by providing a fast fault diagnosis during the product development process and (2) to reduce the cost of testing for high-volume manufacturing. For these reasons, the development of efficient testing techniques for RF systems and components has drawn significant attention in recent years [2-11]. Some of the first proposed schemes for the testing of a wireless transceiver were based on an end-to-end strategy [1] in which the output of the transmitter and the input of the receiver are linked through a loop-back connection. In this configuration, the testing of the complete system is carried out without any external stimulus and employing the available on chip digital hardware. An extension of that approach has been developed for wafer-level test [2]. Other recent efforts on RF systems testing have focused on the development of methodologies and algorithms for automated test [3, 4], and design for testability [5]. Most of the reported transceiver testing techniques have focused on the early detection of catastrophic faults as well as on the time and cost reduction of the overall system verification. However, the characterization of individual building blocks is desirable to detect parametric faults, improve the fault coverage and accelerate the product development phase. Towards this end, BIT techniques are potentially useful, even though their implementation becomes especially difficult for RF circuits. The embedded testing of RF components through alternate test has been explored recently [6-8]. Moreover, in [9], the use of embedded RMS detectors has been shown to be an effective method to test a receiver. This work addresses one of the most difficult challenges in the implementation of BIT techniques for integrated RF components and systems which is to observe high frequency signal paths without affecting the performance of the attached RF building blocks and with low area overhead. The practical on-chip observation of signals in the GHz range through DC measurements can significantly improve the effectiveness and cost-efficiency of the testing of modern integrated communication systems.

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