In many radio systems, particularly those including wide-area functionality like cellular phones, the power amplifier (PA) can represent a significant portion of total transceiver power budget, making its power efficiency crucial to the overall system performance. Unfortunately, despite remarkable recent progress in monolithic CMOS transceiver design, the demands of the PA still make their integration a major challenge. The realization of efficient power amplifiers in standard CMOS is impeded by the technology’s low breakdown voltage, low current drive, large gate capacitance, lossy substrate, and the lack of high-Q monolithic inductors. Low breakdown voltages require the use of a low voltage swing and high current levels are required to provide adequate power; such a low impedance environment is particularly vulnerable to parasitic losses and proper matching with real-world impedances is difficult. Integration with the rest of a transceiver is also a challenge, as power amplifiers can potentially inject substantial noise into the substrate. The resulting interference to other sensitive functional blocks within the system is complex to analyze and hard to simulate.