Characterizing ESD in Integrated Circuits

In order to characterize the susceptibility of a fabricated IC to ESD damage, the
IC must be tested in the laboratory using stimuli which accurately mimic realistic
ESD events. Actual ESD stresses can occur during wafer fabrication, packaging,
testing, or any other time the circuit comes in contact with a person or machine.
The most common industrial tests to measure ESD robustness are the Human-Body
Model (HBM) and the Machine Model (MM) , which are classified based on
the charge storage mechanism. The human-body model, also known as the finger
model, generates a pulse similar to that generated by a electrostatically charged
human directly touching the pins of an IC. On the other hand, the machine model
generates an oscillatory input pulse comparable to a pulse generated when a charged
metal part comes in contact with an IC pin. A typical HBM and MM tester (ORYX
700) .
Some of the other techniques used for ESD characterization include: the Charge Device
Model (CDM) ; field-induced, field-enhanced and capacitive-coupled models;
and a relatively new technique called Transmission Line Pulsing