cadence assura tutorial 2

Introduction to Assura Physical Verification

Assura Physical Verification Tool Suite
Assura Task and Data Flow

Assura Physical Verification Tools, Inputs, and Outputs

Assura Input Files

Creating a Run-Specific File (RSF)
Rule Files

Assura Outputs

Viewing and Interpreting Graphical Results
Viewing Assura Output Text Files
Assura Internal Output Files
Converting Assura Netlists to ASCII
Converting the Layout Netlist to SPICE Format

Invoking Assura

Assura Run-Time Environments
Assura Installation Overview
Running Assura Tools From the DFII GUI
Running Assura in Standalone Graphical Mode
Running Assura in Batch Mode from the UNIX Command Line
Running the Assura Tool Using Remote Job Submission
Creating the Preferences File for Running a Remote Job


Assura Menu Overview

Open Run…
Open Cell…
Rule Sets…
Run DRC…
Run altPSM…
Run LVS…
Open ELW…
Open VLW…
LVS Debug Env…
View Netlist…/Open Schematic Cell…
LVS Error Report…
Short Locator…
Run RCX…
Close Run


Assura DRC and LVS Run-time Options

Specifying Inputs

Input Settings for Assura DRC and LVS
Input Settings for Assura DRC Only
Input Settings for Comparing Two Layouts
Input Settings for Assura LVS Only
Input Settings for LVS and RCX
Input Settings for RCX Only

Preprocessing the Layout

Preprocessing for DRC Only

Controlling the Output

Controlling Output for DRC and LVS
Controlling Output for DRC Only

Controlling Computing Resources
Using the Assura GUI to Set Run-time Options

AvParameters Setup Form
avParameters List
How to Set avParameter Options


DRC Graphical User Interface Run Guide


Preliminary Steps
DRC Run-Specific File
Assura State Files

Assura DRC Run Form

Buttons on Top of the Run Assura DRC Form
Design to be Checked
Run Name and Run Directory
View Rules File and Rule Set
View avParameters
View Additional Functions

Running DRC

Completion of a DRC Run

Viewing the DRC Results

Open Run…
Open ELW…
Open VLW…

Hiding Individual Errors in the Design

Error Corrections
Error Signoffs
Exception File
Exception File Format
Making Error Layers Visible or Invisible in the Design
Zooming, Descending, and Editing in Place


Viewing and Correcting DRC Errors

Steps for Viewing DRC Errors
Set up the VLW, Design Layout Window, and ELW
Select Error Layers
Select the Cell

Using the Arrow Buttons

Open the Error Report

Using the Assura DRC Error Report
Interpreting the Assura DRC Error Report
Assura DRC Error Environments

Display the Error in a Graphics Window
Display Information About Shapes
Display the Summary Report


Comparing Layout and Schematic Netlists

Hierarchical LVS

Correspondence Points

Directing the LVS Run with Compare Rules

Controlling the Run
Specifying the Input Netlists
Specifying Devices
Specifying Cells
Specifying Nets
Specifying Correspondence between Schematic and Layout
Specifying Device and Circuit Reduction
Specifying Device and Circuit Symmetry
Comparing Parameters
Controlling the Output Information

LVS Preprocessing

Processing the Hierarchy
Combining and Permuting MOS Devices
Net Preprocessing
Checking Preprocessing Results

Controlling Pin Swapping

Specifying Cells for Automatic Pin Swap
Limiting Automatic Pin Swapping to Unbound Pins Only
Generating Swap Expressions
Specifying Cell Hierarchies for Swap Analysis
Interaction between autoPinSwap and Other Rules
Using the fix Property in DFII

Optimizing LVS Runtime and Results

Optimize the Layout
How to Avoid Pin Problems
How to Avoid Device-Climbing Problems
How to Avoid and Fix LVS Mismatches with the Binding File
Speed Up Pin Swapping
Expand Cells with Errors

Using Block LVS Techniques
Using Black Box LVS Techniques

Extracting Black Box Cells
Identifying Cells as Black Box Cells for LVS

Comparing Two Schematics


LVS Graphical User Interface Run Guide

Before You Begin

LVS Run-Specific File

Running Assura LVS

Menu Bar
Schematic and Layout Format Information
Run Information
View Rules Files
Viewing and Modifying avParameters
Viewing and Modifying avCompare Rules
Viewing Additional Functions

Viewing Assura LVS Results

Open Run…
Open Cell…
LVS Debug Env…
View Netlist…/Open Schematic Cell…
LVS Error Report…
Short Locator…


Reconciling Layout and Schematic Mismatches

LVS Outputs
Checking the Summary Report
Checking Label Connectivity
Checking the LVS Report

LVS Report Structure
Statistics Section
Instance Pin Errors Section
Bad Initial Net Bindings Section
Bad Net Matches Section
Pin Errors Section
Unmatched Internal Nets Section
Problem Nets Section
Suggested Terminal Rewire Section
Bad Net Connections Section
Unmatched Instances Section
Unmatched Net Details Section
Open Internal Nets Section
Shorted Internal Nets Section
Derived Instances Section

Interpreting the LVS Error Report

Debugging Connection Problems
Debugging Pin-Swapping Problems
Expanding Cells with Errors
Determining that Hierarchies Do Not Match
Accounting for Device Climbing
Verifying an Unfamiliar Layout
Troubleshooting Special Problems

Debugging Graphically


RCX Graphical User Interface Run Guide

RCX/RCX-FS Extraction Matrix
Assura RCX Overview

Assura RCX Extraction Options
Assura RCX GUI Features and Options
How Assura RCX fits in the Assura Physical Verification Flow

How to Access the Assura RCX GUI

Access the Assura Menu
Run Assura LVS or Open an LVS Run
Choose Assura->Run RCX…

The Assura RCX Run Form

Button Bar
Page Up / Page Down
Help Text
RCX Run Form Layout

Setup Tab

Technology Selector and Rule Sets
Using Multiple Rule Sets
Output Format
Spice Output
Spectre Output
Spice / Spectre Options
Extracted View Output
LVS Extracted View Output
Cell-level DSPF Output
Cell-level SPEF Output
Transistor-level DSPF Output
Transistor-level SPEF Output

Extraction Tab

RCX Extraction Modes
How to Input Net Names
RCX-FS Capacitance Extraction
Hierarchical RCX

Filtering Options Tab
Netlisting Options Tab
Run Details Tab

RCX Multiprocessing Section

Substrate Tab
The Assura RCX Run-Specific File

Assura RCX RSF Overview


Substrate Extraction

Setup Substrate Extraction
Substrate Extract Tab
Log Files


Outputting Your Data

Layout Editing or Viewing Flow (Backward Recombination)
Database Merge Using Different Modes


Assura Run-time Resource Allocation

Using Multiple Disks
Using Multiple Processors

Assura Multiprocessing (MP)
Assura Advanced Multiprocessing (AMP)


Virtuoso Phase Designer

Key Product Features and Dependencies
Key Steps in PSM Layout Creation

Phase Shifting Masks

VPD-enabled Design Flow

Insertion of VPD into the Design Flow

VPD Output Sequence
Phase Shifting Mask Rules