analog IC Interview 2

Analog Integrated Circuit techniques

These analog design techniques are also useful for interview preparation
1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t to Vds is low.
2. Present art of analog design still uses the transistor in the saturation region. So one should always keep Vgs of the Transistor 30% above the Vt.
3. One should always split the big transistor into small transistors having width or length feature size <= 15um. 4. W/L Ratio of transistors of the mirror circuit should be less than or equal to 5, to ensure the proper matching of the transistors in the layout. Otherwise, it results to the Systamatic Offset in the circuit. 5. One should make all the required pins in the schmetic before generating the layout view. All IO pins should be a metal2 pins whereas Vdd and Ground should be metal1 pins. 6. One should first simulate the circuit with the typical model parameters of the devices. Since Vt of the trasistor can be anything between Vt(Typical) 20%. So we check our circuit for the extreme cases i.e. Vt + 20%, Vt 20%. A transistor having Vt 20% is called a fast transistor and transistor having Vt+20% is called slow transistor. It's just a way to di erentiate them. So with these fast and slow transistor models we make four combination called nfpf, nfps, nspf, nsps, which are known as process corners. Now, once we are stis.ed with the circuit performance with typical models than we check it in di erent process corners, to take the process variation into account. Vt is just one example of the process variation there are others parameter too. 7. Its thumb rule that poly resistance has a 20% process variation whereas well resistance has got 10%. But the poly resistance has got lower temperature coe.cent and lower Sheet Resistance than well resistance. So we choose the resistance type depending upon the requirments. Poly Capacitance has got a process variation of 10%. 8. One should also check the circuit performance with the temperature variation. We usuly do it for the range of -40C to 85C. 9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells. 10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors. 11. One should place all transistor in layout with a due care to the pinposition before start routing them. 12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible. 13. One should never use POLY as routing layer when the interconnects carries a current. One can have a short gate connection using poly. 14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance. 15. Current in all the transistor and resistor part should ow in the same direction. 16. One should do the Power(Vdd & Gnd) routing in top layer metal (metal5 only). Because Top layer metals are usually thicker and wider and so has low resistance. 17. One should always merge drain and source of transistor (of same type) connected together. 18. To minimize the process variation in the Resistor value one should always take the resistor's width three to four times of the default value. we do it to decrease the value of dR/dL 19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing. 20. One should always make a Common Centroid structure for the matched transistor in the layout. .Each di erential pair transistor should be divide into four transistors and should be placed in two rows common centroid structure. .One may use the the linear common centroid structure for the current mirror circuit. 21. It's advisiable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching. 22. One should always have a Guard Ring arround the di erential pair. 23. Always put a Guard Ring arround the N-well and P-well. 24. Thumb rule for the metal current density is 0:8mA=.m. It's larger for the top most metal layer. 25. To avoid the Latchup, one should always make the PN junction reverse biased i.e. In NWELL should be connected to positive power supply(Vdd) and PWELL should be connected to negative power supply( Gnd). Designers do it to make the leakage current small. 26. It's always a good practice to use a infotext layer to put the name of the device on the top of it in layout and have a netname for every nets in schematic. Designer should put the pin name on the top of the pin with same metaltxt layer because hercuels takes the netname from metaltxt only whereas Diva takes from the pin-name. 27. Cadence SPICE simulator take vdd! & gnd! as a global Vdd and Gnd net i.e. any net ending with ' !' is ocnsidered as a global net..
Common Note : The basic principle is same , but for some notes vary from company to company

methods available to the designer to reduce power consumption in a circuit. The common methods include:
Simplifying the complexity of the circuit Taking conventional architectures and converting them into designs that consume less power Gearing the integrated circuit technology towards low power performance by using, for instance, high Vt processes Decreasing transistor dimensions together with lowering the supply voltage Before delving into power reduction techniques for high speed serial interfaces, consider the case of an operational amplifier as the techniques applied here are pertinent to many other circuit examples. (And also because I know a lot about op-amp design!)
a. The power consumption of the operational amplifier can be reduced by use of an architecture with only a single (differential) stage. This will reduce the current consumption of the device. However, a method of maximizing the gain, whilst preserving an acceptable bandwidth and slew rate are now required in the single gain stage.
b. The output stage could be designed to provide sufficient output drive while quiescently consuming as little power as possible.
c. Optimizing the biasing circuit will reduce the power consumption in the op-amp. This is achieved by reducing the internal stage currents by programming an external current in the form of a resistor outside the integrated circuit. Speed, voltage noise and junction leakage will now become major considerations for the designer as these parameters are affected by the value of the bias current programmed. d. Two important factors that determine the maximum power dissipation in an integrated circuit are the technology used for the design and the type of application. A particular application for CMOS op-amps could be low power switched capacitor filters. If a lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there are two important requirements in the op-amp design. First there must be enough current to charge the compensation capacitor and load capacitor in the required time. Second there must be enough current in the second gain stage transistor to maintain a phase margin of 45º to avoid ringing and degradation of the settling time. If the output current of this circuit is less than the quiescent bias current then this is known as a Class A circuit. There’s a nice write-up in Gray and Meyer.
e. Quiescent power dissipation can be reduced by replacing Class A op-amps with Class AB and dynamic op-amps. The Class AB output stage is designed to be biased at small currents so quiescent power dissipation is correspondingly lower.
f. The basic two-stage differential input op-amp can be designed in the subthreshold current region to minimize the current consumption. The next posting will describe techniques to save power in high speed serial interfaces both in active and sleep/low-power modes.